Two-metal layer ball grid array and chip scale package having local interconnects used in wire-bonded and flip-chip semiconductor assembly

Abstract

The present invention comprises a low cost device ( ) and a method ( ) of forming an electrical interconnect between two metal substrate layers configured in a flip-chip format or a wire bonded format. The invention includes a first metal substrate layer ( ), a second metal substrate layer ( ), and an organic tape layer ( ) attached therebetween as a dielectric. The organic tape layer ( ) includes a series of spaced apart vias ( ) adapted to receive solder paste ( ). The second metal layer ( ) includes a plurality of openings ( ) spaced along the surface thereof and coaxially aligned with the spaced vias ( ). Further, the invention includes a plurality of solder balls ( ) placed across the respective openings ( ) of the second metal layer ( ) such that each solder ball ( ) attaches to the solder paste ( ) forming an electrical interconnect running substantially in parallel between the metal layers ( ). The solder balls are adapted to communicate I/O signals or power to/from an IC supported on the first layer.