The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2004

Filed:

Feb. 26, 2002
Applicant:
Inventors:

Sergey Lopatin, Santa Clara, CA (US);

Alexander H. Nickel, Mountain View, CA (US);

Paul L. King, Mountain View, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7082 ; H01L 2/7102 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/7082 ; H01L 2/7102 ; H01L 2/14763 ;
Abstract

A method of reducing electromigration in a dual-inlaid copper interconnect line ( ) by filling a via ( ) with a Cu-rich Cu—Zn alloy ( ) electroplated on a Cu surface ( from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu—Zn alloy as fill ( ) for the via ( ) in forming the dual-inlaid interconnect structure ( ). The alloy fill ( ) is formed by electroplating the Cu surface ( ) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill ( ) on the Cu surface ( ); and annealing the electroplated Cu—Zn alloy fill ( ); and planarizing the Cu—Zn alloy fill ( ), thereby forming the dual-inlaid copper interconnect line ( ).


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