The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2004
Filed:
Jul. 25, 2001
Chris D. Miller, Austin, TX (US);
TAS Holdings, Inc., Austin, TX (US);
Abstract
Systems and methods are described for an enhanced shared memory unit. Embodiments of methods presented may include permitting a plurality of central processing units to simultaneously read data stored in a first shared memory address. This first shared memory address being accessed by a first central processing unit. These methods may then include receiving a request to read the first shared memory address from a second central processing unit, and receiving a request to read the first shared memory address from a third central processing unit. Furthermore, these methods may then encompass determining a relationship between data stored in the first shared memory address and data stored in a second shared memory address, and determining a relationship between data stored in the first shared memory address and data stored in a third shared memory address. Many of the methods presented also include transforming the data stored in the second shared memory address to a form equivalent to that of the data stored in the first shared memory address, and transforming the data stored in the third shared memory address to a form equivalent to that of the data stored in the first shared memory address. These same methods may also include permitting the second central processing unit to access data stored in the second shared memory address, and permitting the third central processing unit to access data stored in the third shared memory address.
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