High speed random number generation

Abstract

A high-speed random number generator ( ) comprising a physical random number generator, having a data input, an output and a pseudo-random generator coupled to the output of the physical random generator. The pseudo-random generator has an input adapted to receive a germ delivered by the physical generator and deliver at an output a pseudo-random output signal. The physical generator comprises a logic circuit that includes at least a data input (D) and a clock input (CLK), the data input (D) receiving a first “high frequency” clock signal H and the clock input (CLK) receiving a second “low frequency” clock signal H , with the “high frequency” signal H being sampled by the “low frequency” signal H . The two clock signals H and H are of different frequencies respectively and issue from two different first (OSC and OSC ) operating asynchronously from one another and not adhering to the setup time of the logic circuit ( ). The logic circuit is arranged to deliver at an output a signal in an intermediate state qualified as metastable between “0” and “1” and being constituted by a random number sequence. The metastability of the signal obtained as an output from the logic circuit ( ) is accentuated by phase noise of the first oscillator (OSC ) generating the “high frequency” signal H . The pseudo-random generator is arranged to re-inject part of the pseudo-random output signal into the physical generator. An internal memory stores the random numbers obtained as output signals from the pseudo-random generator. The two generators run on the same second “high frequency” clock H generated by the external oscillator ( ).