The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2004

Filed:

Sep. 12, 2002
Applicant:
Inventor:

Yasuaki Hirano, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

In a nonvolatile semiconductor memory device, overerase-verify in an erase operation is conducted in units of bit lines in a batch. A cell current of a reference cell and voltage applied to a word line of a main cell are set so as to have a detection level at which there can be one or no memory cell having a threshold voltage of 0.5 V at time of one overerase-verify operation and a leak current of an unselected memory cell can be 1 &mgr; A or lower in a normal operation. Thus, the number of verify times in the overerase-verify is reduced to shorten period of time in the overerase-verify and thereby achieve high-speed erase. Furthermore, a cell current can be reduced to achieve lower power consumption.


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