Pipelined analog-to-digital converter

Abstract

The present invention is a pipelined analog-to-digital converter (Pipelined ADC) for converting a first analog signal to a digital data. The converter comprises at least one first stage circuit, at least one second stage circuit, a third stage circuit, and a code adder. Each of the first stage circuits has a first converting rate for converting a first analog signal to at least one digital code and generating a second analog signal. The second stage circuits are serially connected after the first stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate for converting the second analog signal to at least two digital codes and generating a third analog signal. The third stage circuit serially connected after the second stage circuits is used for converting the third analog signal to at least one digital code. The code adder is used for combining the digital codes to generate the digital data. Thus, the later half stage circuits of the Pipelined ADC has a higher converting rate, so the converter of the present invention can reduce the number of the stage circuits needed and further reduces the area of the converter.