The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2004

Filed:

May. 28, 2002
Applicant:
Inventors:

Chwan-Ying Lee, Tainan, TW;

Tzuen-Hsi Huang, Tou Liu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer for electroless deposition. The PdSix layer does not require activation. A metal line is formed on a barrier layer and an adhesion layer . A Palladium silicide seed layer is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer to form a metal line. The second embodiment selectively electrolessly deposits metal over an Adhesion layer composed of Poly Si, Al, or Ti. A photoresist pattern is formed over the adhesion layer. A metal layer of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer is removed and the exposed portion of the adhesion layer and the underlying barrier metal layer are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical-mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer and a barrier metal layer over a substrate . The barrier layer is polished and activated. Next, the aluminum layer and the barrier metal layer are patterned. A metal layer is electroless deposited. Next a solder bump is formed over the electroless metal layer


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