The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2004

Filed:

Feb. 18, 2000
Applicant:
Inventor:

Motohide Otsubo, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

Generating a logic circuit indicating an operation result which is easily comparable with an execution result of a program. In step S1, a data flow graph is generated based on only operation sentences of a C program. In step S2, the data flow graph is divided into parts and state names are assigned to the respective parts. In step S3, operations that output a value of an observation variable are detected from the data flow graph. The names of states where the detected operations are performed and the associated observation variables are stored in an observation variable-state list. An FSM is generated in step S4. In step S5, in the FSM, output terminals of an RT level description are added to control signal lines corresponding to the respective states in the list. Data paths are generated in step S6. In step S7, in the data paths, output terminals of an RT level description are added to signal lines corresponding to the respective observation variables in the list. In step S8, RT level data is generated by combining the FSM with the data paths.


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