Metal programmable clock distribution for integrated circuits

Abstract

A method for allowing in-place programming of clock buffer delays of clock buffers in an integrated circuit clock tree is presented. The clock tree comprises at least one clock driver connected between a clock driver input line and a clock driver output line. Each clock driver comprises a plurality of clock buffers connected in series between the clock driver input line and, potentially, the clock driver output line. Metal is reserved in intervening metal layers within a clock driver block between the clock driver input line and the input of a first one of said plurality of clock buffers in the variable clock buffer chain. Metal is reserved on one or more metal layers for connecting the output of each of the clock buffers in the clock buffer chain to the clock driver output line. The metal layers are partitioned into one or more programming layers and one or more non-programming layers. Then, for each clock buffer in the clock buffer chain, an output connection route is mapped between the output of the respective clock buffer to the clock driver output line through the plurality of metal layers. Metal corresponding to the output connection route is then implemented on each of said non-programming layers. During design, a desired clock driver delay for the clock driver is determined. Metal corresponding to the output connection route on each of said programming layers to connect the output of the clock buffer corresponding to the desired delay to the clock driver output line.