Associative processor

Abstract

An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays. The tags logic block supports operations such as logical combinations of match result signals from the CAM cell arrays and the contents of one of the tags registers, with storage of the results in the same tags register or in a different tags register; and also concatenation of two tags registers, with a shift operation applied to the concatenated tags registers resulting in a partial transfer of the contents of one tags register to the other tags register.