Multi-rate clock generator and multi-rate digital data reproducing device

Abstract

In order to construct a PLL circuit corresponding to the plurality of reproduction channel rates by using only a digital loop filter, the generation of a clock in accordance with the reproduction signal, of which the reproduction channel rate varies, is implemented with only one voltage control oscillator in the case when the channel rate of the reproduction signal reproduced from the reproducer varies at n/m of the basic channel rate at the time of recording by allowing the divider to convert the output of the voltage control oscillator , which oscillates at the basic channel rate, into a reproduction clock through the n/m division. The control signal for controlling the voltage control oscillator is generated through the phase error detector and the digital loop filter , and by constructing this digital loop filter with a digital filter which processes using the reproduction clock gained through the n/m division, a PLL circuit with an equal loop delay and loop sensitivity for any data rate can be implemented where, even in the case that the reproduction channel rate varies at a ratio of n/m, the frequency characteristics vary in a similar manner accordingly.