The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2004
Filed:
Jun. 21, 2000
Yasuaki Hirano, Yamatokooriyama, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
For erasing a block , a voltage Vpp is applied to select word lines WL -WL , while a voltage Vneg is applied to each of the substrate (well) and sub-bit lines SBL -SBL . Also, a voltage Vneg is applied to word lines WL -WL of a non-select block , while the voltage Vneg is applied to the substrate (well) and the sub-bit lines SBL. Thus, the voltage Vneg is applied to the control gates, sources and drains of all the memory cells within the non-select block and the substrate (well), so as to make them equal in voltage to one another. Therefore, there occur no mis-reads during the reading. Further, the capacity between the non-select word lines WL and the substrate (well) can be neglected, and the occupancy ratio of the charge pump for use of supply of the negative voltage can be reduced by an extent corresponding to 90% or more of the conventional counterpart. As a result, mis-reads due to substrate disturb during the erasing can be prevented.