Serializer-deserializer circuit having increased margins for setup and hold time

Abstract

A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal. Instead of using the first clock signal input with the data signal, the serializer-deserializer circuit uses a signal, which is generated by an oscillator and thus has a small amount of jitter, as an input clock to the PLL so that a reference clock signal without noise is generated to improve the operation of the serializer-deserializer circuit. In addition, the reference clock signal output from the PLL is locked to the data signal to increase margins for setup and hold time during the latch operation of the data signal.