The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2004

Filed:

Apr. 26, 2001
Applicant:
Inventor:

Subhas Bothra, Fremont, CA (US);

Assignee:

Zeevo, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/06 ; H01L 2/7108 ; H01L 2/994 ;
U.S. Cl.
CPC ...
H01G 4/06 ; H01L 2/7108 ; H01L 2/994 ;
Abstract

A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure. Damascene processes are used to manufacture the multiple metal layer interconnections.


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Bothra, Subhas. (2004). Structure to increase density of mim capacitors between adjacent metal layers in an integrated circuit (U.S. Patent No. 6710425). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6710425

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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