Semiconductor integrated circuit device with enhanced layout

Abstract

There is provided a semiconductor integrated circuit device wherein functional circuit groups are arranged on a chip in a direction spreads, which aims to enhance layout efficiency and to prevent deterioration of element characteristics. A unit wiring region IL P is constituted outside of a power voltage wiring VCC, a part of a second region BIP and a unit wiring region IL N is constituted outside of a reference voltage wiring VSS, a part of a second region BIN. Within the second wiring regions BIP and BIN, connection wirings A, are wired. These connection wirings connect between units within the logic circuits CIA CIR or between the logic circuits CIR CIR There is only arranged an input/output wiring region IOL on a first region A located between the power voltage wiring VCC and the reference voltage wiring VSS Since no unit wiring region exists in the first region A width of the first region A can be laid-out short. Accordingly, connection wiring between PMOS/NMOS transistors can be shortened, areas of an N-type well region NW and a P-type well region PW can be made small. Layout efficiency and circuit characteristic can be enhanced, as a result.