The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2004
Filed:
Sep. 27, 2001
Kazuhiro Satoh, Osaka, JP;
Fumihiro Kimura, Nara, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
Where there are wirings with different film thicknesses or a sheet resistance in a non-scraped state of a wiring layer cannot be obtained as a result of the CPM technique, a wiring resistance according to a film thickness when an LSI is manufactured is acquired by automatic processing to reduce its difference from a real resistance, and accurate voltage drop analysis is carried out to reduce malfunction in a real chip. In a semiconductor circuit device with a plurality of kinds of film thicknesses in the same wiring layer, with a variation occurring in the wiring film thickness when wirings are formed on a silicon wafer, or a warp occurring in an upper layer because the stacking of lower layers is not uniform in the manufacturing process of the wiring, an error of the wiring resistance due to the difference in the film thickness or warp of the wiring is corrected to produce a virtual layout data.