The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2004
Filed:
Feb. 22, 2001
Toshinori Hosokawa, Tokyo, JP;
Masayoshi Yoshimura, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A design for testability is applied so as to enable significant reduction in test time of an actual integrated circuit. First, an integrated circuit is full-scan designed on a block-by-block basis and test input patterns are generated (S ). Then, one of the blocks to which the design for testability has not been allocated is selected (S ), and a full-scan design is allocated thereto (S ). Test points are inserted into a block that has more than a prescribed number of parallel test input patterns when that block is full-scan designed (YES in S ) (S ).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile