The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2004
Filed:
Dec. 28, 2001
Randall Scott Parker, Eau Claire, WI (US);
John Jeffery Wagner, Eleva, WI (US);
Hans Peter Mikelson, Eau Claire, WI (US);
Union Semiconductor Technology Corp., Plymouth, MN (US);
Abstract
A process forms electrical interconnects between memory bits in a magnetoresistive memory device. An initial dielectric layer is formed to overlie a semiconductor substrate. A magnetoresistive storage layer is formed over the initial dielectric layer. An electrically conductive stop layer that is selective to etch processes and is mechanically hard is deposited over the magnetoresistive storage layer. A hardmask layer is formed to overlie the stop layer. The hardmask layer is etched to expose the stop layer. The stop layer and the magnetoresistive storage layer are etched using ion milling until the initial dielectric layer is exposed, defining individual magnetoresistive memory bits. An isolation layer is formed over the hardmask layer and in the etch regions between magnetoresistive bits. The isolation layer is planarized using chemical mechanical polish (CMP) until the stop layer is exposed. An interconnect layer is then formed over the exposed regions of the stop layer and is etched to form electrical interconnects between memory bits.