The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2004

Filed:

Mar. 25, 2002
Applicant:
Inventors:

Hiroshi Inagawa, Maebashi, JP;

Nobuo Machida, Takasaki, JP;

Kentaro Ooishi, Takasaki, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A semiconductor device having an FET of a trench-gate structure is obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate. The trench is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. Thus, the occurrence of a source offset and damage to the gate insulating film is prevented.


Find Patent Forward Citations

Inagawa, Hiroshi. (2004). Method of manufacturing a trench mos gate device (U.S. Patent No. 6706604). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6706604

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…