The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2004

Filed:

Dec. 24, 1997
Applicant:
Inventors:

Anthony C. Bonora, Menlo Park, CA (US);

William J. Fosnight, Austin, TX (US);

Raymond S. Martin, San Jose, CA (US);

Assignee:

Asyst Technologies, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B65G 4/907 ; B25J 1/500 ;
U.S. Cl.
CPC ...
B65G 4/907 ; B25J 1/500 ;
Abstract

An I/O minienvirornent including a port door within an I/O port, and a system for removing the port door and pod door coupled thereto, and setting down the pod and port doors at a convenient location within the I/O minienvironment. After wafer processing has been completed and the wafers have been transferred back through the I/O port to the SMEF pod, the system may retrieve the port and pod doors, and return the port door to their sealing positions within the I/O port and cassette, respectively. In a preferred embodiment, the system for gripping and transporting the port and pod doors may be located on the back end of the end effector of the wafer handling robot within the I/O minienvironment. The back end of the end effector is the end of the end effector opposite that used to transport the wafers and/or cassette.


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