The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2004
Filed:
Sep. 21, 2000
An H. Lam, Houston, TX (US);
Wiley R. Flanakin, Cypress, TX (US);
Sompong Paul Olarig, Cypress, TX (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A digital isolation circuit comprises a plurality of CMOS transistors. The transistors may be connected together to form either a logic NAND gate or a logic NOR gate, but the isolation circuits preferably are not used to provide the NAND or NOR logic functions. The isolation circuit isolates one input data signal from an output signal in response to a control input signal. If the control signal is driven to one state (e.g., logic ), the isolation circuit can be made to function as an inverter when no isolation is needed. In the opposite logic state, the control signal causes the isolation circuit to isolate the input data signal from the output signal.