The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2004
Filed:
Jul. 18, 2000
Ming-Tung Shen, Taipei City, TW;
Other;
Abstract
A multi-chip semiconductor module includes first and second substrates. The first substrate has opposite first and second surfaces, a plurality of first conductive vias that extend through the first and second surfaces, and a first circuit layout patterned on the second surface and connected electrically to the first conductive vias. The second substrate has opposite first and second surfaces, a plurality of second conductive vias that extend through the first and second surfaces of the second substrate, a second circuit layout patterned on the second surface of the second substrate and connected electrically to the second conductive vias, and a chip-receiving opening formed therein. The first surface of the second substrate is bonded on the second surface of the first substrate such that the second circuit layout is connected electrically to the first circuit layout through the first and second conductive vias. A first semiconductor chip is disposed in the chip-receiving openings, and has a first contact pad surface mounted on the second surface of the first substrate and formed with a plurality of first contact pads that are connected to the first circuit layout. A second semiconductor chip has a second contact pad surface mounted on the second surface of the second substrate and formed with a plurality of second contact pads that are connected to the second circuit layout.