The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2004

Filed:

Jul. 17, 2000
Applicant:
Inventor:

Misao Suzuki, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 2/300 ;
U.S. Cl.
CPC ...
H04L 2/300 ;
Abstract

A phase adjusting circuit for a semiconductor memory includes a D/A converter which includes a D/A converting circuit receiving code signals A to An, and a current mirror circuit having an input transistor P connected to an output node S of the D/A converting circuit and an output transistor P for supplying an output current lout. A switch circuit is connected between a gate of the input transistor P and a gate of an output transistor P , and a capacitor is connected to the gate of an output transistor P . The switch circuit is turned off before the code signals A to An applied to the D/A converting circuit change, and after a fluctuation of the potential on the output node S of the D/A converting circuit has been settled, the switch circuit is turned on, with the result that a hazard occurring in the D/A converting circuit is prevented from being transferred to the current mirror circuit . When the switch circuit is in an off condition, the capacitor holds the potential before the code signals A to An changes, so that the output current Iout before the code signals A to An changes, is maintained.


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