The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2004

Filed:

Aug. 29, 2001
Applicant:
Inventors:

Jeongwoo Lee, Seoul, KR;

Yido Koo, Seoul, KR;

Kang Yoon Lee, Seoul, KR;

Eunseok Song, Seoul, KR;

Hyungki Huh, Kyung-Ki-Do, KR;

Joonbae Park, Seoul, KR;

Kyeongho Lee, Seoul, KR;

Assignee:

GCT Semiconductor, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 ; H03L 7/06 ;
U.S. Cl.
CPC ...
H03D 3/24 ; H03L 7/06 ;
Abstract

A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.


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