Programmable logic device and method of controlling clock signal thereof

Abstract

An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being generated and retaining a processing speed of the device. To this end, according to the present invention, there is provided a device including logic blocks for carrying out logical operation, lines for connecting the logic blocks, line-changing means for changing the state of lines connecting the logic blocks by programming, a clock net for supplying a clock signal to each of the logic blocks, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of the logic blocks can be stopped from being supplied with the clock signal.