The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2004
Filed:
Jul. 20, 2000
Applicant:
Inventor:
Eric Fischer, Eau Claire, WI (US);
Assignee:
Silicon Graphics, Inc., Mountain View, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method, system, and program product for designing and verifying an electronic circuit. A circuit logic design is translated into a netlist using a synthesis tool. The synthesis tool receives inputs of placing, routing, and timing information. Timing delays in the logic design are represented in the netlist using the placing and routing information. It is determined whether a timing goal has been reached based on the timing delays. When the timing goal has not been reached, changes are made to the placing, routing, and timing information, and the synthesis tool is re-executed using the changed information until the timing goal is reached.