The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2004
Filed:
Feb. 18, 1999
John G McBride, Ft Collins, CO (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A method and apparatus for evaluating an integrated circuit design to determine whether a pass FET is part of a RAM cell structure in the integrated circuit design. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a pass FET in the integrated circuit is part of a RAM cell structure of the integrated circuit. The rules checker program of the present invention evaluates each pass FET which is channel-connected at one of its terminals to a latch node and determines whether that pass FET is channel-connected at one of its other terminals to the drain or source terminal of at least one other pass FET. If so, the pass FET being evaluated is part of a RAM cell structure. In accordance with the preferred embodiment of the present invention, the rules checker program evaluates nodes in an integrated circuit to detect latch nodes. When a latch node is detected, the rules checker program determines whether or not a single pass FET is connected by either its drain or source terminal to the latch node. If so, the rules checker program obtains the pointer to the other drain or source terminal of the pass FET. The rules checker program then obtains a list of elements that are channel-connected to the node designated by the pointer and searches the list to determine whether or not more than one pass FET is contained in the list. If so, the rules checker program determines that the pass FET connected to the latch node is part of a RAM cell structure as opposed to a latch structure.