The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6700430 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 02, 2004

Filed:

Aug. 20, 2002
Applicant:
Inventors:

Mario M. Pelella, Mountain View, CA (US);

Srikanth Sundararajan, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/704 ;
U.S. Cl.
CPC ...
H03K 1/704 ;
Abstract

A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.


Find Patent Forward Citations

Pelella, Mario. (2004). Method to reduce time to dynamic steady-state condition (U.S. Patent No. 6700430). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6700430

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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