The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2004
Filed:
Dec. 04, 2001
Joseph D. Wert, Arlington, TX (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An extended voltage range level shifter is provided that includes an input inverter and first and second circuit branches. The input inverter includes thin-gate devices, is coupled to an internal power supply, and is operable to receive internal data and to generate inverted internal data. The first circuit branch includes a p-type, thick-gate transistor that has a source coupled to an external power supply; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage that is less than the external power supply and greater than the internal power supply; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data. The second circuit branch also includes a p-type, thick-gate transistor that has a source coupled to the external power supply, a drain coupled to a gate of the p-type transistor for the first circuit branch, and a gate coupled to the drain of the p-type transistor for the first circuit branch; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive the reference voltage; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the inverted internal data.