Conditioning circuit for selectively buffering an input signal to a signal processing circuit, and a signal processing circuit incorporating the conditioning circuit

Abstract

A signal processing circuit comprising an ADC ( ) to which differential signals and pseudo-differential signals are switched through two multiplexors ( ) and ( ). Positive input signals are buffered to a positive input terminal ( ) of the ADC ( ) through a buffer ( ). Negative input signals are buffered through a conditioning circuit ( ) to a negative input terminal ( ) of the ADC ( ). The conditioning circuit ( ) comprises a buffer circuit ( ) having a buffer ( ), through which input signals are selectively buffered to the negative input terminal ( ) of the ADC ( ), and a bypass circuit ( ) which bypasses the buffer circuit ( ) for selectively passing input signals unbuffered to the negative input terminal ( ) of the ADC . First and second primary switches ( ) and ( ) are selectively operated in response to a primary switching signal from a control circuit ( ) for selecting one of the buffer circuit ( ) and the bypass circuit ( ) in response to channel select signals for the multiplexors ( ) and ( ) so that input signals, the voltage of which falls outside the operating voltage of the buffer ( ) are passed unbuffered directly to the negative input terminal ( ) through the bypass circuit ( ). The control circuit ( ) instead of being responsive to a channel select signal may be arranged to be responsive to the voltage of the input signals for operating the first and secondary primary switches ( ). Two conditioning circuits ( ) may be provided one for each input terminal to the ADC ( ).