The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6696864 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 24, 2004

Filed:

Oct. 09, 2002
Applicant:
Inventors:

Shunzo Yamashita, Tokorozawa, JP;

Kazuo Yano, Hino, JP;

Yasuhiko Sasaki, Menlo Park, CA (US);

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9094 ;
U.S. Cl.
CPC ...
H03K 1/9094 ;
Abstract

This application proposes a new logic circuit including the 1st selector (S ) in which the control input S is controlled by the first input signal (IN ), the input I or I is controlled by the second input signal (IN ), and the output O is connected to the first node (N ), and the 3rd selector (S ) in which the control input S is controlled by the first node (N ), the input I is controlled by the third input signal (IN ), the input I is controlled by the first input signal (IN ), and the output is connected to the first output signal (OUT ).


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Yamashita, Shunzo. (2004). Logic circuit and its forming method (U.S. Patent No. 6696864). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6696864

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