The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2004

Filed:

Nov. 29, 2000
Applicant:
Inventor:

Akihiko Yoshizawa, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 2/312 ; G01R 2/320 ; H03D 1/300 ;
U.S. Cl.
CPC ...
G01R 2/312 ; G01R 2/320 ; H03D 1/300 ;
Abstract

An integrated circuit for testing a PLL circuit that includes a phase error generator to receive a signal gained by dividing an oscillated signal from a voltage controlled oscillator and a reference signal so as to detect a phase error signal between the both, an integrating circuit to integrate error signals outputted by the phase error generation circuit, a reference voltage generator to generate a predetermined reference voltage, and a comparator configured to compare an integration result voltage outputted from the integrating circuit with a reference voltage generated by the reference voltage generation circuit, wherein the reference voltage generator and the comparison circuit is configured electrically outside of a loop in the PLL circuit.


Find Patent Forward Citations

Yoshizawa, Akihiko. (2004). Integrated circuit and lot selection system therefor (U.S. Patent No. 6696828). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6696828

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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