The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2004

Filed:

Oct. 05, 2000
Applicant:
Inventor:

Hide Hattori, Palo Alto, CA (US);

Assignee:

Pericom Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 ;
U.S. Cl.
CPC ...
H03D 3/24 ;
Abstract

A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two VCO inputs. The DAC's two reference-voltage inputs are connected to these VCO inputs. The DAC's output voltage is selected from within the voltage range between the two VCO voltages by a digital code-word input to the DAC. The DAC's output voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the digital code-word input to the DAC.


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