The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2004

Filed:

Mar. 22, 2000
Applicant:
Inventors:

Eric G. Stevens, Rochester, NY (US);

William F. Desjardin, Holley, NY (US);

Assignee:

Eastman Kodak Company, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/335 ;
U.S. Cl.
CPC ...
H04N 5/335 ;
Abstract

A structure for a fast-dump gate for charge coupled devices that does not require a separate contact to a drain region instead using the existing drain of a lateral overflow drain (LOD) typically used for antiblooming purposes. LOD structures are typically used on full-frame CCD image sensors. By using the LOD as the drain for a fast-dump gate, a separate opening in the gate electrode for the drain contact is avoided, thereby making the structure more compact. Gate control is provided by etching a hole in the CCD gate electrode over the overflow channel region of the LOD structure, and overlaying this with one of the subsequent gate electrode layers. This subsequent gate electrode is then used to control the fast-dump operation. Timing is shown for a two-phase CCD being operated with accumulation-mode clocking. Other types of CCDs and clocking schemes may be used. Another advantage of this structure is that it does not require any additional masking or processing steps when built, using a double electrode CCD process that employs a typical LOD structure.


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