The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2004

Filed:

Sep. 06, 2000
Applicant:
Inventor:

Tatsumi Mitsushita, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 1/140 ;
U.S. Cl.
CPC ...
G06T 1/140 ;
Abstract

A processing circuit capable of realizing an operation including a logarithm of 2 operation with a small scale circuit configuration, wherein a priority encoder and a shaft circuit normalize g data, a table outputs &mgr;=“log ({1, qm})−qm” corresponding to a mantissa qm, another shift circuit shifts data obtained by bit coupling a data maxe comprised by only an integer part and a &mgr; data toward the MSB by L, another shift circuit shifts data obtained by bit coupling an exponent qe and the mantissa qm toward the MSB by L, an adder circuit adds &dgr;2, &ggr;2, and {K, 3′b0, 10}, and a clamp circuit clamps the result of addition to a predetermined number of bits.


Find Patent Forward Citations

Mitsushita, Tatsumi. (2004). Reduction rate processing circuit and method with logarithmic operation and image processor employing same (U.S. Patent No. 6693634). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6693634

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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