The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2004
Filed:
Jan. 14, 2003
Applicant:
Inventors:
Watanabe Masayuki, Yokohama, JP;
Sugano Toshio, Kokubunji, JP;
Tsukui Seiichiro, Komoro, JP;
Ono Takashi, Akita, JP;
Wakashima Yoshiaki, Kawasaki, JP;
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/302 ; H01L 2/940 ;
U.S. Cl.
CPC ...
H01L 2/302 ; H01L 2/940 ;
Abstract
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
Masayuki, Watanabe. (2004). Semiconductor memory module having double-sided stacked memory chip layout (U.S. Patent No. 6693346). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6693346
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile