The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Apr. 21, 2000
Jörg Henkel, Princeton, NJ (US);
Wayne Wolf, Princeton, NJ (US);
Haris Lekatsas, Princeton, NJ (US);
Other;
Abstract
A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions. The invention also has an apparatus utilizing a post-cache architecture that has a decompression engine that decompresses instructions that have been compressed using the method of the invention. The apparatus extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.