Processor interfacing to memory-centric computing engine

Abstract

Methods and apparatus are disclosed for interfacing a processor bus or CPU to a computation engine to carry out selected tasks with improved efficiency in the computation engine. The computation engine is controlled by an MCC memory-centric controller that provides microcoded operation of the engine independently of the CPU. Essential interfacing between the processor bus and the computation engine includes storing microcode in a separate memory accessible to the MCC controller, or downloading microcode from the CPU/processor bus as needed for a specific task. The MCC controller can reconfigure the computation engine, such as memory block allocation, word size, etc. under microcode control, so that new or user-proprietary algorithms such as those used in dsp can be implemented using a standard computation engine without redesign. Execution of selected tasks on the computation engine is triggered automatically by decoding instructions that appear on the processor bus. Such tasks can include dsp, compression, decompression, encryption or other complex computations, and further can include downloading new or updated microcode into the computation engine desired.