The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2004

Filed:

Feb. 15, 2002
Applicant:
Inventor:

Peter S. Guilfoyle, Zephyr Cove, NV (US);

Assignee:

Opticomp Corporation, Zephyr Cove, NV (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/28 ; G02B 6/34 ; G02B 6/42 ;
U.S. Cl.
CPC ...
G02B 6/28 ; G02B 6/34 ; G02B 6/42 ;
Abstract

A virtual distributed optical crossbar local area network configuration where the central switch or network controller has been eliminated. A virtual distributed optical crossbar allows a network to be fully scalable as the number of users increases. The virtual distributed optical crossbar is fully non-blocking and is reconfigurable. In addition the virtual distributed optical crossbar has zero latency across the network, employs vertical cavity surface emitting laser technology and smart pixel technology in conjunction with a resonant cavity enhanced (RCE) waveguide grating coupler (WGC). Optical signals are transmitted through fiber optic and/or waveguide or freespace interconnects implementing the switching functions. The waveguide technology provides the enabling mechanism to achieve a zero latency, fully non-blocking, performance. Address decoding functions between processors is divided, leaving only the true distance interconnect implemented by optical means. Unique to this architecture is it eliminates the central switches and servers within telecommunications networks. The architecture is clock rate reconfigurable performing crossconnect switching within single clock cycles.


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