The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2004

Filed:

Apr. 09, 2003
Applicant:
Inventors:

Andre Schäfer, München, DE;

Joachim Schnabel, München, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 ;
U.S. Cl.
CPC ...
G11C 7/10 ;
Abstract

A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.


Find Patent Forward Citations

Schäfer, Andre. (2004). Logic signal level converter circuit and memory data output buffer using the same (U.S. Patent No. 6690605). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6690605

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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