The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2004

Filed:

Nov. 29, 2001
Applicant:
Inventors:

Eiichi Hasegawa, Tokyo, JP;

Kazuhisa Oyama, Tokyo, JP;

Masahisa Kimura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 5/32 ;
U.S. Cl.
CPC ...
H03B 5/32 ;
Abstract

An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV and the inversion potential (1.8 volts) of a CMOS inverter IV the logical output value of a CMOS Schmitt inverter SI is 1. The output of a CMOS inverter formed by MOS transistors T and T is shorted out via a MOS transistor T Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV or the inversion potential of the CMOS inverter IV is exceeded, if the input voltage to the CMOS Schmitt trigger SI increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T and T is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.


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