The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Jun. 19, 2002
Mukesh Nair, Pune, IN;
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
A multiple voltage environment input pad with a circuit input comprises a level shifter circuit (A) and a buffer circuit (B). The buffer circuit B comprises an inverter comprising at least two transistors ( ) of opposite types, followed by twin controllable voltage dividers ( ) of opposite types. Each controllable voltage divider ( ) has at least two controllable voltage divider inputs and a controllable voltage divider output. For each of the controllable voltage dividers ( ) one of the inputs is connected to an output ( ) of the level shifter circuit (A) and another one of the inputs is connected to an output ( ) of the inverter. For each of the controllable voltage dividers ( ) the voltage divider output is connected to a current input connection of a transistor ( ) of corresponding type of the inverter. The level shifter circuit (A) comprises a series pass transistor ( ) and in parallel thereto a transistorized capacitor ( ). Furthermore a transistorized capacitor ( ) is connected between the output of the inverter and the output of one of the two controllable voltage dividers ( ).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile