The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Sep. 25, 2002
Kenneth Smetana, San Diego, CA (US);
Applied MicroCircuits Corporation, San Diego, CA (US);
Abstract
A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee ) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. The CML circuit has an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by the first power supply and a third power supply (Vee ) that is approximately equal to Vcc−(0.4+(level of series gated logic)(0.9 volts)).