The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2004

Filed:

Oct. 07, 1999
Applicant:
Inventors:

Dana How, Palo Alto, CA (US);

Adi Srinivasan, Fremont, CA (US);

Abbas El Gamal, Palo Alto, CA (US);

Assignee:

Lightspeed Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9177 ; G06F 7/38 ;
U.S. Cl.
CPC ...
H03K 1/9177 ; G06F 7/38 ;
Abstract

A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.


Find Patent Forward Citations

How, Dana. (2004). Function block architecture for gate array (U.S. Patent No. 6690194). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6690194

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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