The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Sep. 21, 2000
Chun Jiang, San Jose, CA (US);
Yowjuang Bill Liu, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method for forming a uniformly planarized structured in a semiconductor wafer forms metal structures on a substrate layer with spaces between the structures. The top surfaces of the metal structures lie within a common plane. Dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is then deposited on the layer, the metal structures and in the spaces. The dielectric layer is then subjected to a second etching. Further deposition and etching steps are performed until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.