The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Sep. 22, 1999
Kevin Lyne, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A modeling technique for selectively depopulating solder balls ( ) (and their respective solder ball pads ( ), vias ( ) and traces or lines ( )) from a conventional foot print of a ball grid array (BGA) package, or land grid array package (LGA) to improve device reliability. The modeling technique anticipates a routing of traces through the gap resulting from the depopulated solder balls or lands as additional space for routing traces or lines from solder ball or land pads to an exterior surface of a substrate ( ) upon which a semiconductor die ( ) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls or lands on ever shrinking packages, thereby increasing device reliability.