The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
Jul. 12, 2001
Kazunori Sakamoto, Katano, JP;
Hideo Hatanaka, Katano, JP;
Yukihiro Ishimaru, Hirakata, JP;
Tosaku Nishiyama, Nara, JP;
Abstract
A multilayer wiring board comprising a mother wiring board and a carrier wiring board, in which all of the composing layers have IVH structure. The mother wiring board ( ) is formed in the manner that a plurality of resin-impregnated-fiber-sheets having mother wiring layers ( ) and first inner-via-hole conductors ( ) for connecting the wiring layers ( ) each other are laminated. The mother wiring board ( ) comprises a base board ( ) and container board ( ) having an opening for forming a cavity ( ). The carrier wiring board ( ) has lands ( ) for mounting LSI bare chips, wirings ( ), a plurality of carrier-board-wiring-layers ( ) and second inner-via-hole conductors ( ) for connecting the wiring layers ( ) each other. The carrier wiring board ( ) is set in the cavity ( ) for electrically connecting the carrier wiring board ( ) to the mother wiring board ( ) by connecting carrier board electrodes ( ) to mother board electrodes ( ) through connectors ( ) of solder balls, gold bumps or electrically conductive paste. The carrier wiring board ( ) has higher wiring density at the portion where LSI bare chips are mounted, than the mother wiring board.