Wide frequency range pll clock generating circuit with delta sigma modulating circuitry for reducing the time changing ratio of the input voltage of a voltage controlled oscillator

Abstract

A clock generation circuit of the present invention extracts a phase error signal of a digital signal obtained from a recording medium ( ) by a phase comparator ( ), filters the phase error signal by a loop filter ( ). In a first embodiment it converts the signal into an analog signal by a minute control D/A converter ( ), detects whether the signal is within a set range by a range detector ( ), generates a modulation reference signal by a modulation reference signal generator ( ), modulates the modulation reference signal by a pulse width modulator ( ), adds a frequency set value and the modulation reference signal by an adder ( ), converts the addition result into an analog signal by a rough control D/A converter ( ), cuts high-band components of the analog signal by a low-pass filter ( ), adds the analog signals output from the minute control D/A converter ( ) and the low-pass filter ( ) by an analog adder ( ), and outputs a clock signal by a voltage controlled oscillator ( ) on the basis of an output signal of the analog adder ( ). Thereby, a clock signal which can continuously lock a wide frequency range can be generated. In a second embodiment the loop filter output is oversampled ( ), then interpolated ( ) and modulated by a multivalued delta sigma modulator.