Multi-channel dma with request scheduling

Abstract

A digital system is provided with a multi-channel DMA controller ( ) for transferring data between various resources ( ). Each channel includes a source port ( ), a channel controller ( ) and a destination port ( ). Channel to port buses (CP -CP ) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC -PC ) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry ( ) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller ( ) on each clock cycle for providing an address for a transaction performed on each clock cycle. The schedulers operate in parallel and source/destination channel addresses are transferred in parallel to each scheduler via the parallel channel to port buses. Input/output data words are also transferred in parallel to/from each port. Each port is tailored to provide an access protocol required by its associated resource. The ports may be tailored to provide an access protocol required by a different type of resource. Channel and scheduling circuitry within a sub-portion ( ) of the DMA controller can interact with various versions of tailored ports without being modified.