The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2004

Filed:

Jun. 06, 2002
Applicant:
Inventor:

Esther Vega Ordonez, München, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/134 ;
U.S. Cl.
CPC ...
G11C 1/134 ;
Abstract

To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a plurality of memory blocks ( ) that each memory block ( ) has a corresponding data bus and a group of sense amplifiers ( ) connected to this data bus ( ) associated with it. In this way it is possible for the bus-line capacitance (C ), which contributes to the total bit-line capacitance, to be reduced because the bus-line capacitance then depends simply on the length of a memory sector ( ).


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Vega Ordonez, Esther. (2004). Semiconductor memory arrangement (U.S. Patent No. 6687163). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6687163

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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